Opis: CADENCE LIRARIES/INTRFC MAINT
Opis: INTEGRAPH SCHEM SYNTH/SIM LIBRA
Opis: EXEMPLAR SYNTHESIS LIBS/INTRFC
Opis: SYNOPSYS LIBRARIES/INTRFC MAINT
Opis: INTEGRAPH SCHEM SYNTH/SIM MAINT
Opis: SYNOPSYS LIBRARIES/INTRFC MAINT
Opis: MENTOR V8 LIBRARIES/INTRFC MAINT
Opis: CADENCE VERILOG LIB/INTRFC MAINT
Opis: EXEMPLAR SYNTHESIS LIBS/INTRFC
Opis: FPGA DESIGN SYS W/VWDRAW/VIEWSIM
Opis: ATMEL SYNARIO VERILOG SIM OPTION
Opis: ATMEL SYNARIO VHDL SYNTHESIS OPT
Opis: ATMEL SYNARIO VHDL SYNTHESIS OPT
Opis: MENTOR V8 LIBRARIES/INTERFACE
Opis: UNIV AT6000 PHYSICAL DESIGN SYS
Opis: FPGA DESIGN SYSTEM W/VIEWDRAW
2025/05/20