Opis: MAINT FPGA 20K GA VIEWLOGIC SYS
Opis: INTEGRAPH SCHEM SYNTH/SIM MAINT
Opis: INTEGRAPH SCHEM SYNTH/SIM LIBRA
Opis: MENTOR V8 LIBRARIES/INTERFACE
Opis: DESIGN SYS PWRVIEW/SIMUL 20K GAS
Opis: CADENCE LIRARIES/INTRFC MAINT
Opis: EXEMPLAR SYNTHESIS LIBS/INTRFC
Opis: ATMEL SYNARIO VHDL SYNTHESIS OPT
Opis: EXEMPLAR SYNTHESIS LIBS/INTRFC
Opis: ATMEL SYNARIO VERILOG SIM OPTION
Opis: MENTOR V8 LIBRARIES/INTRFC MAINT
Opis: SYNOPSYS LIBRARIES/INTRFC MAINT
Opis: INTEGRAPH SCHEM SYNTH/SIM LIBRA
Opis: ATMEL SYNARIO VHDL SYNTHESIS OPT
Opis: CADENCE VERILOG LIB/INTRFC MAINT
2025/05/20